In recent electronic devices such as a mobile phone and a digital camera, the functional enhancement and the reduction in size and weight of the electronic devices are important, and as the electronic components for their achievement, the highly functional, small-sized and thin electronic components have been required. Therefore, the density increase by the scaling-down of a large scale integrated circuit (LSI) of a semiconductor chip mounted in electronic components and the density increase by the system in package (SiP) technology as the package structure have been proceeding.
However, for the further scaling-down of the LSI, the LSI manufacturing line has to be modified, and an enormous amount of capital investment is required. Further, problems such as leakage current and others have become more obvious due to the scaling-down, and the deviation of the performance enhancement from the theoretical value also occurs in some cases.
In the SiP structure, a plurality of LSIs are mounted on an intermediate substrate called interposer substrate and sealed with resin, and chip electrodes and electrodes of the interposer substrate are connected by wire bonding using Au wires in many cases. The wire bonding is effective for the electrical connection because the lines of wires are flexibly changed. As a method of reducing the mounting area, the case where the chip mounted immediately above the interposer substrate is flip-chip bonded by Au bumps, solder bumps or ACF (Anisotropic conductive film) with an active element surface of the chip directed to the interposer substrate side has also been increasing.
Therefore, although the thickness of the chip and substrate has to be reduced and the pitch of the electrodes has to be narrowed for the further density increase and downsizing of the electronic component with the SiP structure, they have become difficult from the perspective of the manufacturing limit of the intermediate substrate mainly made of an organic substrate, the limit of thinning wires such as Au wires and the reliability of the wire bonding in a miniaturized region. Furthermore, in the electronic components for mobile devices, the demands for lower power consumption have been sharply increasing. Since each of the chips is connected through the intermediate substrate in the SiP structure, the SiP structure has the problem of large power consumption in addition to the long wiring length and the difficulty in high-speed transmission.
As described above, the measures by means of the density increase by the scaling-down of the LSI and the density increase by the SiP technology cannot sufficiently satisfy the increasing demands for the functional enhancement, the downsizing and the lower power consumption.
In such a circumstance, the three-dimensional LSI Package has attracted attention as one solution for the problem described above. In this three-dimensional LSI Package, upper and lower semiconductor chips and wiring boards are electrically connected by using through-silicon vias, and it is effective for the high-speed transmission and the reduction in power consumption because the wiring length can be reduced. Further, since the mounting area can be reduced, it is advantageous also for the downsizing. Therefore, various types of methods have been proposed for the stacking connection of the upper and lower chips and wiring boards (for example, Patent Documents 1 to 3).
Japanese Patent Application Laid-Open Publication No. 2005-51150 (Patent Document 1) describes a stack method of semiconductor chips. The chips are stacked in each chip mounting position of a semiconductor substrate in which a plurality of chip mounting regions are determined. Thereafter, the stacked chips are sealed with a sealing material. Then, the semiconductor substrate is cut at predetermined positions outside the chip mounting regions, thereby separating it into a plurality of semiconductor devices.
Japanese Patent Application Laid-Open Publication No. 2008-135553 (Patent Document 2) describes a substrate stacking method. It provides a substrate stacking method capable of facilitating the handling of the substrate by suppressing the warpage of the substrate when stacking the substrate. In this method, after connecting the substrates, the substrate is reduced in thickness by grinding the rear surface until the through electrodes are exposed.
Japanese Patent Application Laid-Open Publication No. 2007-234841 (Patent Document 3) describes a connection method at a low bonding temperature. In this method, the conductive layer is connected to the conductor made of indium via an intermediate layer containing copper-indium alloy, and the bonding temperature can be set lower than that of the case of using solder alloy bumps such as Sn-3.5Ag.